# HiFive1 Rev B

**Type:** Product page · **SKU:** CE07319 · **Brand:** [Maker Community](https://core-electronics.com.au/brands/maker-community)
**Page:** https://core-electronics.com.au/hifive1-rev-b-47614.html ([markdown](https://core-electronics.com.au/hifive1-rev-b-47614.html.md))

## Retired product

This product is retired and no longer available for purchase. Replaced by: DFR0640.

**Replacement:** https://core-electronics.com.au/catalog/product/view/sku/DFR0640

## Description

he FE310-G002 is an upgrade to the Freedom Everywhere SoC, that adds support for the latest RISC-V Debug Spec 0.13, hardware I²C, two UARTs, and power gating the core rail in low power sleep modes. Like the original FE310, the FE310-G002 features SiFive’s E31 CPU core complex, a high-performance, 32-bit RV32IMAC core with a 16 KB L1 instruction cache, a 16 KB data SRAM scratchpad, and hardware multiply/divide. Running at 320+ MHz, the FE310 is among the fastest microcontrollers on the market.

The HiFive1 dev board has also been upgraded. Powered by the FE310-G002, the new HiFive1 Rev B has wireless connectivity through an onboard Wi-Fi/Bluetooth module. The USB debugger has been upgraded to Segger J-Link, with support for drag & drop code download. In favor of driving GPIO directly from the FE310, the HiFive1 Rev B supports 3.3 V I/O only.

**Features**

- Open Source RTL: The FE310 is the first open-source, commercially available RISC-V SoC. SiFive has contributed the FE310 RTL code to the open-source community. Now you can see what’s inside the chip and completely understand how the hardware works. [Take a look](https://github.com/sifive/freedom). By releasing the RTL code, SiFive wants to encourage open source development of both software that runs on RISC-V, as well as new RISC-V-based hardware. The RTL code empowers chip designers with the ability to customize their own SoC on top of the base FE310. For system architects, developers, or companies without chip design capabilities, SiFive’s "chips-as-a-service" can customize the FE310 to meet their unique needs.
- More Peripherals: With this second-generation version, the FE310 chip now has a built-in hardware I²C peripheral and an extra UART (two total), which opens the door to connect to all sorts of third-party sensors, actuators, and other devices. In addition, the USB debug interface has been upgraded to Segger J-Link.
- Low-power Sleep Mode: The FE310-G002 has an Always-On (AON) power domain powered from 3.3 V. Controlled by AON, the CPU core power rail (1.8 V) can be turned off in sleep mode and will be turned on upon detecting a wake event.
- Wireless Co-processor: The HiFive1 Rev B board has both Wi-Fi and Bluetooth capabilities, thanks to a single-core ESP32 co-processor that serves as a wireless modem for the FE310-G002 processor.

**Specifications**

Chipset

- CPU: SiFive E31
- RISC-V Debug Spec: [Version 0.13](https://core-electronics.com.au/attachments/localcontent/riscv-debug-spec-0_65079dcb938.pdf)
- Low-Power Sleep Mode: Yes
- Always-on Domain: 3.3V
- Hardware I2C: 1
- UART: 2
- QSPI/SPI: 1/1 with 3 chip selects
- PWM: 9
- GPIO: 19

Development Board

- Processor: SiFive FE310-G002
- USB Debug: Segger J-Link
- Wireless Network: Wi-Fi & Bluetooth
- Low-power Domain: Yes
- I/O Voltage: 3.3V
- Code Storage\*: 4MB QSPI NOR Flash
- Form Factor: 68x51mm

*\* The original HiFive1’s 16 MB of code storage was overkill — there’s still plenty of room in 4 MB.*

**Resources**

- [RISC-V Debug Specification Version 0.13](https://core-electronics.com.au/attachments/localcontent/riscv-debug-spec-0_65079dcb938.pdf)
- [SiFive Developer Portal](https://dev.sifive.com/)
- [SiFive Freedom GitHub Repository](https://github.com/sifive/freedom)

## Images

- [Product image 1](https://core-electronics.com.au/media/catalog/product/h/i/hifive1-revb-angle-04_png_project-body.jpg)